1. Technical Field of the Invention
The invention relates to a memory controller, and more particularly, to a memory controller capable of precisely controlling data output time.
2. Description of the Related Art
In many computer systems, a memory controller is used to efficiently manage the read and write transactions between a processor (or processors) and one or more random access memory (RAM) devices. Some memory controllers has a buffer (e.g., FIFO memory) that temporarily stores data to make data writing in a flash memory and data reading therefrom smoother. To perform a data output (read) operation synchronized with the operational clock (external clock) of a host system, the memory controller may need to compensate for memory access latency. When the memory device detects a falling edge of a read-enable signal RE, a read operation starts in the memory device. An activated read-enable (RE) signal (e.g., transmitted through the memory controller to the memory device) enables the memory device to output (read out) stored data, and the activated read-enable signal may then propagate back through the memory controller to indicate or control the availability of valid read data. Read data may not be instantaneously available (output) from some memory devices at the same time that the read-enable signal is activated. The access time TREA of a memory depends upon the characteristics of the individual memory device. Some memory devices may have different memory access latencies TREA, such that read data may be output (available) later from some memory devices than from others. Thus, there is a need for a memory controller capable of variably delaying the propagation of a read-enable signal and read data in the memory controller.
Delay lines are used within digital circuits such as board level systems and integrated circuit (1C) devices, including field programmable gate arrays (FPGAs) and microprocessors, to control the timing of various signals in the digital circuits. A simple delay line receives an input signal on an input terminal and provides an output signal on an output terminal, the output signal being a copy of the input signal delayed by a certain time period that is referred to as the delay D of the delay line. More complicated delay lines are tunable (e.g., digitally programmable) so that delay D of the delay line can be adjusted.